Software Verification for Embedded Systems

Embedded systems have the characteristics of reactive, real-time, distributed systems. For these kind of systems formal veri£cation is by nature complex, even more since the system interaction with its environment is often modeled, e.g., as hybrid systems. However, every embedded control system will certainly fail, if its software fails. In this work we present an approach to the formal veri£cation of Programmable Logic Controller (PLC) software. We present a tool that translates PLC programs written in the language Sequential Function Charts automatically into an abstract model that can be read by a standard model checker. Moreover, we demonstrate its effectiveness by an application to a sorting plant and show that software veri£cation can indeed contribute to system reliability.